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Picture 1: DC-Measurement of integrated MOS-transistors and extraction of the model parameters for simulation models
The picture 1 shows a comparison of an fitted MOS-model (EKV-model with lines) with the measurement
dates of an 0.65um process (dots). Because of the geometry control included in MOS-models,
the represented model fit of one geometry (width=3um, length=3um) is to repeat and ensure on
every other geometry. In the case of high quality demands on the geometry control (e.g.
analog applications) an test wafer have to provide up to 15 transistors for both channel
types with different length and width. The following picture shows a width- and length-partitioning
for an CMOS-transistor-pair, which considers the demands of extracting the geometry control
parameters.
Picture 2: Width- and length-partitioning in an assessment system:
For determination of the AC-parameters, additional test structures are required to carry
out CV-measurements (among other things).
Offer for integrated MOS-transistors: