Lateral Bipolar transistors are also important in the new and modern integration
technologies. Beside their usage in standard bipolar processes this elements are
used in standard CMOS and BiCMOS processes. All this structures are showing the
most unwished parasitic effects, because in standard processes special technological
steps like buried layer and deep sinker are missed. Because of that an accurate
modeling of this elements with inclusion of the Parasitics is a important goal.
Following simple example is showing an pnp Lateral transistor produced in a full
implanted technology. Because of the insufficient isolation technique for this
device a heavily substrate effect is obtained. In a conventional CMOS technology
lateral transistors are showing more unfavourable behaviour. Following picture
shows a comparison of measured and simulated data of all the three dependent
currents Ib, Ic/Ie and Is in forward and reverse mode.
It is recognizable that in forward mode the substrate current is moderate, but
in reverse mode the model without substrate current gives an large error in
current gain over a wide emitter current range.
Although the inverse mode is not big deal, it must noticed that in saturation
case the collector current component has some influence. The following
example shows the result of a simple current mirror (without corrector)
simulation - in this case the output transistors working in saturation.
In compare the two simulation results we obtain an additional mirror error
of about 2% in normal mode, but more than 15% in saturation case only from
the bad modelling of substrate effect. If the used isolation technique is more
unfavourable, this result is more worse.
Although this small example shows more the DC-behaviour of the pnp structures, it should be explained that the physical effects also have influence on the AC-behaviour of the transistor, which most used as active loads in circuit design. Furthermore, the model make it possible to calculate substrate currents of whole circuit blocks, which are used in analysis of latch-up effects in BiCMOS technology.
The used macromodel in this example can also apply to the modelling of npn
transistors. The source code exist for all important SPICE simulators and
can easy parametrized because of his simple structure.