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Device- and Process Characterisation

IBIS - Modeling

What are IBIS - models and what can we do with that?

IBIS (I/O-buffer information specification) - models are a standardized method to describe the electrical behavior of the interface of complex logical devices. So it is possible, to make an analysis of signal integrity on board level by including parasitic effects. The main difference to SPICE - modeling on device - or macro - level is a standard form description of the I/O behavior, so the device supplier don't give a look inside his circuitry and the EDA - Tools software house has a fixed model interface for simulation purpose. The user of the simulator has the advantage for higher speed in simulation for large systems with a small loss of accuracy compare to SPICE.

What does this model look?

• Following elements are the basic elements after IBIS - version 2.1:
  1. Pull-down element
  2. Pull-up element
  3. Description of rise - and fall times
  4. Protection circuits
  5. Case and pin parasitics

  The electrical behavior of the pull elements and the protection circuit is described with a one dimensional table. Following picture shows as a example the output characteristic of IC's CGS74B2525N from National Semiconductor Corporation.

  

  Remarkable for this curve is the large registered range, which is extended over the normal used range. This guarantee real simulation also with worse termination. Furthermore the IBIS - description contains worst case for technological deviations, so this cases can also analyzed.

• Which I/O types and which technologies are supported?
  IBIS - version 2.1 contains following I/O types:
  1. Input/Output Buffer
  2. Open Drain/Collector stages
  3. Open source/sink stages
  4. Bidirektionale Buffer
  5. TRI-state buffer
  6. Terminators

  With the following technologies a large range of modern IC technologies is supported:

  1. CMOS
  2. TTL
  3. ECL/PECL
• Which simulators are supporting IBIS - models?
  The following EDA provider are supporting IBIS models in their simulators for signal integrity analysis:

  Interconnectix

  Quad Design Technologies

  HyperLynx

  Cadence

  Viewlogic

DAnalyse offer for IBIS-Modeling

If you a user of one above programs or an other program which support the IBIS interface and you are missing the description of one or more IC'c so we can do it. The investigation of relevant data we make with our measurement equipment and a verification compared to a SPICE simulation.

But also without special simulators IBIS models are interesting for the simulation of critical paths in PCB design. With the own developed method of table look up based simulation this models can also used in SPICE like simulators. Please contact us!